1. Field of the Invention
The present invention relates to an integrated circuit (hereinafter referred to as “IC”) and more particularly to a circuit with variation correction function, which suppresses variation of output characteristic regardless of variation of characteristic of components due to manufacturing reason so as to obtain an output near a desired characteristic value. For example, preferably, the present invention is applied to such mobile communication device as a portable phone.
2. Description of Related Art
Recently, reduction of the quantity of required components has been demanded in many electronic device fields, which is represented by such a mobile communication device as a portable phone. For example, in case of the aforementioned mobile communication device, if its oscillation circuit is incorporated in an IC, this contributes to the reduction of the quantity of its components. FIG. 16 shows a voltage control oscillation circuit (hereinafter referred to as “VCO circuit”) as an example of such an oscillation circuit. The VCO circuit of FIG. 16 contains a resonant circuit comprising an inductor section 101 and a capacitor section 102. Its oscillation frequency f is given by a following equation with inductance L of the inductor section 101 and capacitance C of the capacitor 102.
[Expression 1]
  f  =      1          2      ⁢      π      ⁢              LC            
The capacity of a variable capacitor in the capacitor section 102 can be changed by control voltage VT. Thus, the oscillation frequency f can be adjusted according to the control voltage VT. A phase lock loop (hereinafter referred to as “PLL”) is constituted of such a VCO circuit. Upon use, the oscillation frequency f of the VCO circuit is made to coincide with a setting frequency of PLL.
However, if the aforementioned VCO circuit is incorporated in an IC, following problems occur. That is, characteristic values of incorporated elements vary unavoidably on manufacturing process of the IC. Consequently, the oscillation characteristic of the VCO circuit varies. This will be explained with reference to a graph of FIG. 17. This graph indicates an oscillation frequency f while the control voltage VT is raised from 0.5 V to 2.5 V. This graph further indicates five results that the capacitance C of the capacitor section 102 is finished to −20%, −10%, ±0%, +10%, +20%.
Here, it is assumed that the setting frequency of the PLL is set to 620 MHz. Then, a following matter becomes evident from the graph of FIG. 17. If this circuit is finished as its specification indicates or to ±0%, the control voltage VT for acquiring an output of the setting frequency is 1.6 V. Contrary to this, if the circuit is finished to −20%, the control voltage VT is 1.0 V. On the other hand, if it is finished to +20%, the control voltage VT in this case is 2.2 V, which is different from the preceding case by 1.2 V. The variation of the oscillation characteristic appears as a variation of the control voltage VT when the PLL is locked.
If the capacitance C of the capacitor section 102 is larger or smaller, the oscillation frequency band of the VCO circuit may be deflected completely from the lock range of the PLL. In this case, the PLL locking fails, so that the system cannot be used as desired. Further, even if the oscillation frequency band exists within the lock range, if the control voltage VT is extremely higher or lower than its normal value, the loop characteristic of the PLL is different from its ordinary characteristic. Thus, the phase noise characteristic may deteriorate or lock-up time until the oscillation frequency is locked to the setting frequency may take longer. In the meantime, a similar problem, which may be generated by manufacturing characteristic variation, exists not only in the capacitance of the capacitor device but also in other kinds of devices.